Ars Technica

Breaking into ASIC Design/Verification

I'm fast approaching the one year mark with my current employer since I graduated last year. Previously, I did three four month work terms with them and they were for the most part interesting. I took ...
Design-Reuse

Cadence Boosts Verification Productivity for Complex FPGA/ASIC Design

SAN JOSE, Calif. -- Jan 10, 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, today announced significant new advancements to help boost ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM ...

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Design-Reuse

ChipMaestro from eInfochips Extends SoC Design and Verification Expertise to Computer ...

New service leverages 500+ man-years of expertise in designing and verifying complex chips Expanded service offering enables customers to focus limited resources on core competencies Santa Clara, CA - ...
Electronic Design

Manage ASIC, SoC Design Risk with Leading-Edge Verification Services

Managing challenges and risks that accompany a complex SoC design with FPGA prototyping and verification is critical in reducing or eliminating product delays and associated costs. Value in design ...
Electronic Design

The Reality Of ESL Is Mixed-Abstraction Design And Verification

For a decade now, mainstream complex ASIC design and verification has been done at one level of abstraction. Logic is captured, tests are generated, simulations are analyzed, and IP is delivered at ...
Semiconductor Engineering

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools

Digital systems need clocks. Today’s designs require more from clocking schemes than ever before, and it’s likely this trend will continue. Increasing power constraints have resulted in finer-grained ...
EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design Solutions Center, NEC Electronics ...
EDN

SystemVerilog 3.1 adds assertions and testbench automation

The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. It eliminates many of Verilog's past limitations, ...
Semiconductor Engineering

Overcoming Low Power Verification Challenges For Mixed-Signal SoC Designs

Isolation, retention, and power switches are the important functionalities of power-aware designs which use the common low power techniques like power shutoff, multi-voltage, and advanced techniques ...
Nasdaq

Faraday Adopts Synopsys SpyGlass Design Handoff Kit to Ensure High Design Quality

MOUNTAIN VIEW, California, July 1, 2019 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced that Faraday Technology Corporation, a leading fabless ASIC and IP provider, has adopted Synopsys' ...
NextBigFuture

Low Energy and Super-Efficient AI Chips

Taalas and Etched are two AI chip startups aiming to challenge Nvidia’s dominance in the AI hardware market. Etched is using ASIC chips. Taalas is using eASIC chips. They are both putting the logic ...